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ISL21009MEP
Data Sheet December 15, 2008 FN6744.0
High Voltage Input Precision, Low Noise FGATM Voltage References
The ISL21009MEP FGATM voltage references are extremely low power, high precision, and low noise voltage references fabricated on Intersil's proprietary Floating Gate Analog technology. The ISL21009MEP features very low noise (4.5VP-P for 0.1Hz to 10Hz), low operating current (180A, Max), and 3ppm/C of temperature drift. In addition, the ISL21009 family features guaranteed initial accuracy as low as 0.5mV. This combination of high initial accuracy, low power and low output noise performance of the ISL21009MEP enables versatile high performance control and data acquisition applications with low power consumption.
Features
* Specifications per DSCC VID V62/08629 * Full Mil-Temp Electrical Performance from -55C to +125C * Controlled Baseline with One Wafer Fabrication Site and One Assembly/Test Site * Full Homogeneous Lot Processing in Wafer Fab * No Combination of Wafer Fabrication Lots in Assembly * Full Traceability Through Assembly and Test by Date/Trace Code Assignment * Enhanced Process Change Notification * Enhanced Obsolescence Management * Eliminates Need for Up-Screening a COTS Component * Output Voltages . . . . . . . . . . . . . . 2.500V, 4.096V, 5.000V * Initial Accuracy . . . . . . . . . . . . . . . . . . . . .0.5mV, 1.0mV * Input Voltage Range. . . . . . . . . . . . . . . . . . . 3.5V to 16.5V * Output Voltage Noise . . . . . . . . .4.5VP-P (0.1Hz to 10Hz) * Supply Current . . . . . . . . . . . . . . . . . . . . . . . .180A (Max) * Temperature Coefficient . . . . . . . . . . . . 3ppm/C, 5ppm/C
Device Information
The specifications for an Enhanced Product (EP) device are defined in a Vendor Item Drawing (VID), which is controlled by the Defense Supply Center in Columbus (DSCC). "Hot-links" to the applicable VID and other supporting application information are provided on our website.
Available Options
VOUT OPTION (V) 2.500 2.500 4.096 5.000 5.000 INITIAL ACCURACY (mV) 0.5 1.0 0.5 0.5 1.0 TEMPCO. (ppm/C) 3 5 3 3 5
* Output Current Capability. . . . . . . . . . . . . . . Up to 7.0mA * Operating Temperature Range. . . . . . . . . -55C to +125C * Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld SOIC
PART NUMBER ISL21009BMB825EP ISL21009CMB825EP ISL21009BMB841EP ISL21009BMB850EP ISL21009CMB850EP
Applications
* Defense/Commercial Avionics * Radar/Sonar Systems * Signal Processing Applications
Pinout
ISL21009MEP (8 LD SOIC) TOP VIEW GND or NC 1 VIN 2 DNC 3 GND 4 8 DNC 7 DNC 6 VOUT 5 TRIM or NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. FGA is a trademark of Intersil Corporation. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL21009MEP Pin Descriptions
PIN NUMBER 1 2 4 5 6 3, 7, 8 PIN NAME GND or NC VIN GND TRIM VOUT DNC DESCRIPTION Can be either Ground or No Connect Power supply input connection Ground connection Allows user trim typically 2.5%. Leave unconnected when unused. Voltage reference output connection Do Not Connect; Internal connection - must be left floating
Ordering Information
PART NUMBER (Note 1) ISL21009BMB825EP ISL21009CMB825EP ISL21009BMB841EP ISL21009BMB850EP ISL21009CMB850EP NOTE: 1. Add "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. PART MARKING 21009BM 25EP 21009CM 25EP 21009BM 41EP 21009BM 50EP 21009CM 50EP VOUT OPTION (V) 2.500 2.500 4.096 5.000 5.000 GRADE 0.5mV, 3ppm/C 1.0mV, 5ppm/C 0.5mV, 3ppm/C 0.5mV, 3ppm/C 1.0mV, 5ppm/C TEMP. RANGE (C) -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 PACKAGE 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC PKG. DWG. # M8.15 M8.15 M8.15 M8.15 M8.15
1 +5V C1 10F 2 3 4
GND VIN NC GND ISL21009-25EP
NC NC VOUT NC
8 7 6 5
SPI BUS X79000 1 2 3 4 5 6 7 8 9 10 SCK A0 A1 A2 SI SO RDY UP DOWN OE CS CLR VCC VH VL VREF VSS VOUT VBUF VFB 20 19 18 17 16 15 14 13 12 11 LOW NOISE DAC OUTPUT C1 0.001F
FIGURE 1. TYPICAL APPLICATION PRECISION 12-BIT SUB-RANGING DAC
2
FN6744.0 December 15, 2008
ISL21009MEP Typical Performance Curves (ISL21009-25EP) (REXT = 100k)
140 UNIT 1 120 100 IIN (A) 80 60 40 20 0 3.5 5.5 7.5 9.5 VIN (V) 11.5 13.5 15.5 80 3.5 5.5 7.5 9.5 VIN (V) 11.5 13.5 15.5 UNIT 3 IIN (A) 110 UNIT 2 +25C +125C 120
100 -40C 90
FIGURE 2. IIN vs VIN, 3 UNITS
FIGURE 3. IIN vs VIN, 3 TEMPERATURES
VOUT (V) (NORMALIZED TO 2.50V AT VIN = 5V)
2.50010 2.50005 2.50000 UNIT 1 2.49995 2.49990 2.49985 2.49980 3.50 UNIT 3 VOUT (mV) NORMALIZED TO VIN = 5.5V UNIT 2
100 -55C 50 0 -50 -100 -150 -200 3.5 +25C +125C
5.50
7.50
9.50 11.5 VIN (V)
13.5
15.5
5.5
7.5
9.5 VIN (V)
11.5
13.5
15.5
FIGURE 4. LINE REGULATION
FIGURE 5. LINE REGULATION OVER-TEMPERATURE
0.1 VOUT (mV) NORMALIZED TO VIN = 5.5V 0.05
+125C
2.5002 2.5001 2.5000 VOUT (V) UNIT 3
0 -0.05 -0.1 -0.15 -7
+25C
2.4999 2.4998 2.4997 2.4996 -55C 2.4995 2.4994 UNIT 2 UNIT 1
-5 SINKING
-3
-1
1
3
5 SOURCING
7
2.4993 -40
-20
0
20
40
60
80
100
120
140
OUTPUT CURRENT (mA)
TEMPERATURE (C)
FIGURE 6. LOAD REGULATION
FIGURE 7. VOUT vs TEMPERATURE
3
FN6744.0 December 15, 2008
ISL21009MEP Typical Performance Curves (ISL21009-25EP) (REXT = 100k)
0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 1 10 100 1k 10k 100k 1M 10M 100nF 10nF 1nF 500kHz PEAK VIN (DC) = 10V NO LOAD
(Continued)
FREQUENCY (Hz)
FIGURE 8. PSRR AT DIFFERENT CAPACITIVE LOADS
FIGURE 9. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
5.2 4.8 4.4 4.0 3.6 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 0
VIN HIGH IIN
VIN AND VOUT (V)
MEDIUM IIN LOW IIN 0.05 0.10 0.15 0.20 TIME (ms) 0.25 0.30 0.35 0.40
FIGURE 10. LINE TRANSIENT RESPONSE, 0.001F LOAD CAPACITANCE
FIGURE 11. TURN-ON TIME
160 140 120 ZOUT () 100 80 60 40 20 0 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 1nF NO LOAD 100nF 2mV/DIV 10nF
GAIN IS x1000, NOISE IS 4.5VP-P
FIGURE 12. ZOUT vs FREQUENCY
FIGURE 13. VOUT NOISE, 0.1Hz TO 10Hz
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FN6744.0 December 15, 2008
ISL21009MEP Typical Performance Curves (ISL21009-25EP) (REXT = 100k)
NO OUTPUT CAPACITANCE
(Continued)
NO OUTPUT CAPACITANCE
7mA +50A
-50A -7mA
FIGURE 14. LOAD TRANSIENT RESPONSE
FIGURE 15. LOAD TRANSIENT RESPONSE
Typical Performance Curves (ISL21009-41EP) (REXT = 100k)
110 105 95 100 IIN (A) IIN (A) UNIT 3 95 UNIT 2 90 UNIT 1 85 80 5 7 9 11 VIN (V) 13 15 17 80 5 7 9 11 VIN (V) 13 15 17 85 90 +125C -40C +25C 100
FIGURE 16. IIN vs VIN, 3 UNITS
FIGURE 17. IIN vs VIN, 3 TEMPERATURES
VOUT (V) NORMALIZED TO 4.096V AT VIN = 5.0V
4.0963 4.0962 4.0962 4.0961 4.0961 4.0960 4.0960 4.0959 4.0959 4.0958 4.50 6.50 8.50 10.5 VIN (V) 12.5 14.5 16.5 UNIT 3 UNIT 1 UNIT 2 VOUT (mV) NORMALIZED TO VIN = 5.5V
200 150 100 50 0 -50 +125C 6.5 8.5 10.5 VIN (V) 12.5 14.5 16.5 -55C +25C
-100 4.5
FIGURE 18. LINE REGULATION, 3 UNITS
FIGURE 19. LINE REGULATION OVER-TEMPERATURE
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FN6744.0 December 15, 2008
ISL21009MEP Typical Performance Curves (ISL21009-41EP) (REXT = 100k)
0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -7 +125C -6 -5 -4 -3 -2 -1 0 1 2 SINKING OUTPUT CURRENT (mA) -55C 3 4 5 6 7 SOURCING +25C VOUT (V) NORMALIZED TO 4.096V 0.6 VOUT (mV) NORMALIZED TO VIN = 5.5V 4.0970 4.0965 4.0960 UNIT 2 4.0955 UNIT 3 4.0950 4.0945 -40 UNIT 1 -25 -10 5 20 35 50 65 80 95 110 125
(Continued)
TEMPERATURE (C)
FIGURE 20. LOAD REGULATION
FIGURE 21. VOUT vs TEMPERATURE
0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 1nF LOAD -80 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) X = 10s/DIV Y = 200mV/DIV 10nF LOAD VIN (DC) = 5V VIN (AC) RIPPLE = 50mVP-P NO LOAD 100nF LOAD
FIGURE 22. PSRR AT DIFFERENT CAPACITIVE LOADS
FIGURE 23. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
VIN
VREF
X = 10s/DIV Y = 200mV/DIV
X = 50s/DIV Y = 2V/DIV
FIGURE 24. LINE TRANSIENT RESPONSE, 0.001F LOAD CAPACITANCE
FIGURE 25. TURN-ON TIME
6
FN6744.0 December 15, 2008
ISL21009MEP Typical Performance Curves (ISL21009-41EP) (REXT = 100k)
200 180 160 140 ZOUT ( ) 120 100 80 60 40 20 0 1 10 100 1k 10k 100k 1M 10M 1s/DIV FREQUENCY (Hz) 10nF LOAD NO LOAD 1nF LOAD 20mV/DIV
(Continued)
GAIN IS x10,000 NOISE IS 4.5VP-P
FIGURE 26. ZOUT vs FREQUENCY
FIGURE 27. VOUT NOISE, 0.1Hz TO 10Hz
7mA +50A
-50A -7mA NO OUTPUT CAPACITANCE X = 5s/DIV Y = 50mV/DIV NO OUTPUT CAPACITANCE X = 5s/DIV Y = 500mA/DIV
FIGURE 28. LOAD TRANSIENT RESPONSE
FIGURE 29. LOAD TRANSIENT RESPONSE
7
FN6744.0 December 15, 2008
ISL21009MEP Typical Performance Curves (ISL21009-50EP) (REXT = 100k)
140 UNIT3 120 100 IIN (A) 80 60 40 20 0 5.50 6.50 7.50 8.50 9.50 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VIN (V) 80 5.50 6.50 7.50 8.50 9.50 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VIN (V) UNIT1 IIN (A) UNIT2 110 +25C
100 +125C 90 -40C
FIGURE 30. IIN vs VIN, 3 UNITS
FIGURE 31. IIN vs VIN, 3 TEMPERATURES
VOUT (V) (NORMALIZED TO 5.0V AT VIN = 10V)
5.0001 VOUT (mV) NORMALIZED TO VIN = 5.5V 5.0000 4.9999 4.9998 UNIT2 4.9997 4.9996 4.9995 UNIT1 UNIT3
100 50 0 -50 -100 -150 -200 -250 -300 -350 -400 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VIN (V) +25C -55C +125C
4.9994 5.50 6.50 7.50 8.50 9.50 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VIN (V)
FIGURE 32. LINE REGULATION
FIGURE 33. LINE REGULATION OVER-TEMPERATURE
0.10 VOUT (mV) NORMALIZED TO VIN = 5.5V 0.05 0 +25C -55C +125C
-0.05 -0.10 -0.15 -0.20 -7 -6 -5 -4
-3
-2
-1
0
1
2
3
4
5
6
7
SINKING
OUTPUT CURRENT (mA)
SOURCING
FIGURE 34. LOAD REGULATION
8
FN6744.0 December 15, 2008
ISL21009MEP Typical Performance Curves (ISL21009-50EP) (REXT = 100k)
5.001 NORMALIZED TO +25C 5.001 PSRR (dB) 5.000 VOUT (V) UNIT 2 5.000 4.999 4.999 4.998 -40 UNIT 3 -20 0 20 40 60 80 100 120 140 UNIT 1 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 10 100 1k 10k 100k 1M 10M 100nF 1nF 10nF VIN (DC) = 10V VIN (AC) RIPPLE = 50mVP-P NO LOAD
(Continued)
TEMPERATURE (C)
FREQUENCY (Hz)
FIGURE 35. VOUT vs TEMPERATURE
FIGURE 36. PSRR AT DIFFERENT CAPACITIVE LOADS
VIN = 10V DVIN = 1V VIN = 10V DVIN = 1V
FIGURE 37. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
FIGURE 38. LINE TRANSIENT RESPONSE, 0.001F LOAD CAPACITANCE
12 VIN (V) AND VOUT (V) 10 8 6 4 2 0 0 270nA 50 VIN ZOUT (W) 450nA
120 1nF 100 80 60 NO LOAD 40 340nA 100 150 TIME (s) 200 250 300 20 0 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10nF
FIGURE 39. TURN-ON TIME
FIGURE 40. ZOUT vs FREQUENCY
9
FN6744.0 December 15, 2008
ISL21009MEP Typical Performance Curves (ISL21009-50EP) (REXT = 100k)
GAIN IS x1000 NOISE IS 4.5VP-P
(Continued)
50A
2mV/DIV
-50A
FIGURE 41. VOUT NOISE, 0.1Hz TO 10Hz
FIGURE 42. LOAD TRANSIENT RESPONSE
7mA
-7mA
FIGURE 43. LOAD TRANSIENT RESPONSE
Applications Information
FGA Technology
The ISL21009MEP voltage reference uses floating gate technology to create references with very low drift and supply current. Essentially the charge stored on a floating gate cell is set precisely in manufacturing. The reference voltage output itself is a buffered version of the floating gate voltage. The resulting reference device has excellent characteristics, which are unique in the industry: very low temperature drift, high initial accuracy, and almost zero supply current. Also, the reference voltage itself is not limited by voltage bandgaps or zener settings, so a wide range of reference voltages can be programmed (standard voltage settings are provided, but customer-specific voltages are available). The process used for these reference devices is a floating gate CMOS process and the amplifier circuitry uses CMOS transistors for amplifier and output transistor circuitry. While 10
providing excellent accuracy, there are limitations in output noise level and load regulation due to the MOS device characteristics. These limitations are addressed with circuit techniques discussed in other sections.
Micropower Operation
The ISL21009MEP consumes extremely low supply current due to the proprietary FGA technology. Low noise performance is achieved using optimized biasing techniques. Supply current is typically 95A and noise is 4.5VP-P benefitting precision, low noise portable applications such as handheld meters and instruments. Data Converters in particular can utilize the ISL21009MEP as an external voltage reference. Low power DAC and ADC circuits will realize maximum resolution with lowest noise.
FN6744.0 December 15, 2008
ISL21009MEP
Board Mounting Considerations
For applications requiring the highest accuracy, board mounting location should be reviewed. The device uses a plastic SOIC package, which will subject the die to mild stresses when the PC board is heated and cooled, slightly changing the shape. Placing the device in areas subject to slight twisting can cause degradation of the accuracy of the reference voltage due to these die stresses. It is normally best to place the device near the edge of a board, or the shortest side, as the axis of bending is most limited at that location. Mounting the device in a cutout also minimizes flex. Obviously mounting the device on flexprint or extremely thin PC material will likewise cause loss of reference accuracy.
Turn-On Time
The ISL21009MEP devices have low supply current and thus the time to bias up internal circuitry to final values will be longer than with higher power references. Normal turn-on time is typically 100s. This is shown in Figure 11. Circuit design must take this into account when looking at power-up delays or sequencing.
Temperature Coefficient
The limits stated for temperature coefficient (tempco) are governed by the method of measurement. The overwhelming standard for specifying the temperature drift of a reference is to measure the reference voltage at two temperatures, take the total variation, (VHIGH - VLOW), and divide by the temperature extremes of measurement (THIGH - TLOW). The result is divided by the nominal reference voltage (at T = +25C) and multiplied by 106 to yield ppm/C. This is the "Box" method for specifying temperature coefficient.
Noise Performance and Reduction
The output noise voltage in a 0.1Hz to 10Hz bandwidth is typically 4.5VP-P. The noise measurement is made with a bandpass filter made of a 1-pole high-pass filter with a corner frequency at 0.1Hz and a 2-pole low-pass filter with a corner frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth. Noise in the 10kHz to 1MHz bandwidth is approximately 40VP-P with no capacitance on the output. This noise measurement is made with a 2 decade bandpass filter made of a 1-pole high-pass filter with a corner frequency at 1/10 of the center frequency and 1-pole low-pass filter with a corner frequency at 10x the center frequency. Load capacitance up to 1000pF can be added but will result in only marginal improvements in output noise and transient response. The output stage of the ISL21009MEP is not designed to drive heavily capactive loads, so for load capacitances above 0.001F, the noise reduction network shown in Figure 44 is recommended. This network reduces noise significantly over the full bandwidth. Noise is reduced to less than 20VP-P from 1Hz to 1MHz using this network with a 0.01F capacitor and a 2k resistor in series with a 10F capacitor. Also, transient response is improved with higher value output capacitor. The 0.01F value can be increased for better load transient response with little sacrifice in output stability.
.
Output Voltage Adjustment
The output voltage can be adjusted up or down by 2.5% by placing a potentiometer from VOUT to GND and connecting the wiper to the TRIM pin. The TRIM input is high impedance so no series resistance is needed. The resistor in the potentiometer should be a low tempco (<50ppm/C) and the resulting voltage divider should have very low tempco <5ppm/C. A digital potentiometer such as the ISL95810 provides a low tempco resistance and excellent resistor and tempco matching for trim applications.
VIN = 5.0V 10F 0.1F VIN VO ISL21009-25EP GND 0.01F 10F 2k
FIGURE 44. HANDLING HIGH LOAD CAPACITANCE
11
FN6744.0 December 15, 2008
ISL21009MEP Typical Application Circuits
VIN = +5.0V R = 200 2N2905 VIN VOUT ISL21009MEP VOUT = 2.50V GND
2.5V/50mA 0.001F
FIGURE 45. PRECISION 2.5V, 50mA REFERENCE
+3.5V TO 16.5V 0.1F 10F
VIN VOUT ISL21009-25EP VOUT = 2.50V GND
0.001F VCC RH + EL8178 - RL VOUT (BUFFERED) VOUT (UNBUFFERED)
X9119 SDA 2-WIRE BUS SCL VSS
FIGURE 46. 2.5V FULL SCALE LOW-DRIFT, LOW NOISE, 10-BIT ADJUSTABLE VOLTAGE SOURCE
12
FN6744.0 December 15, 2008
ISL21009MEP Typical Application Circuits (Continued)
+3.5V TO 16.5V 0.1F 10F
VIN VOUT ISL21009-25EP GND + -
EL8178 VOUT SENSE LOAD
FIGURE 47. KELVIN SENSED LOAD
+3.5V TO 16.5V 0.1F
10F
VIN VOUT ISL21009-25EP TRIM GND
2.5V 2.5%
VCC I2C BUS SDA SCL ISL95810 VSS
RH
RL
FIGURE 48. OUTPUT ADJUSTMENT USING THE TRIM PIN
13
FN6744.0 December 15, 2008
ISL21009MEP Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
a
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6744.0 December 15, 2008

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